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| ASIC Design Verification |
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| Hardware Design: |
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| Currently involved in the verification of ASICs. These ASICs are targeted toward the communication industry and are in the area of Asynchronous Transfer Mode (ATM) and Packet Over Sonet (POS). |
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| System Controller for MIPS 64 bit processor |
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| Complete design of system controller FPGA. This FPGA interfaces with MIPS 64 bit processors and has a 32 bit, 33 MHz PCI bus controller, DMA engine, Interrupt controller and timers. Xilinx FPGA was used for this purpose. |
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| Reference Design for NEC MIPS RISC processors |
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| Designed reference platforms for MIPS R5000 processor. The evaluation platform has the processor running at 200 MHz internal frequency and 100 MHz bus speed. The system controller has built-in SDRAM controller with ECC and PC100 DIMM support, a PCI Master/slave controller for 64 bit, 66 MHz operation for up to 5 masters, scatter-gather DMA and timers/interrupt controllers. In addition the board has Flash, EPROM, Ethernet, 16550C Serial ports, Parallel port and PCI slots. |
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| VxWorks Board Support Package for R5000 reference design |
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| Adapted the PMON PROM monitor and VxWorks BSP for the R5000 reference design. Includes implementation of a variety of drivers: polled mode serial I/O, serial I/O, Fast Ethernet, clocks/timers, and timestamp. Supports host connection either though serial and Ethernet connection using PPP and FTP. |
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